The vsi alliance (vsia), a non-profit, leading Semiconductor ip standards organization and Chip Estimate Corporation recently announced that they will work




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IP Gains Quality Rating -- The VSI Alliance (VSIA), a non-profit, leading Semiconductor IP standards organization and Chip Estimate Corporation recently announced that they will work together to provide IP integrators with a unified website for locating, searching and selecting IP cores from companies who have adopted the QIP Metric from the VSI Alliance. The site can be found at www.ChipEstimate.com
Over the next few months, Chip Estimate will supplement their IP catalog with a listing of IP cores to which the QIP Metric has been applied, as this information is made available by the IP vendors. Once the QIP data has been incorporated, users will be able to locate cores that are QIP-rated allowing engineers to determine which core best addresses their design needs. Additionally, designers can download the InCyte tool at ChipEstimate.com to explore the effects of different IP within a design and to estimate chip die size, power and leakage.
In less than seven months of providing public access to the QIP Metric -- which currently addresses Soft IP cores and vendor assessment- the VSIA has recorded over 1000 unique user downloads. Jointly, the FSA and VSIA are developing the Hard IP evaluation metric that will be available soon. Providing public access to QIP scores through the ChipEstimate.com IP portal will further drive adoption of the QIP Metric in the SoC design process and ultimately result in more predictable, cost-effective and reusable designs. For more information, visit the VSIA web site at www.vsi.org or visit the Chip Estimate web site at www.ChipEstimate.com.

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Support Grows for IP -- The SPIRIT Consortium, a global non-profit organization focused on establishing multi-faceted IP/tool integration standards that drive sustainable growth in electronic design, today announced the addition of 16 new companies to its membership roster. The Consortium attributes this significant growth in its membership over the past few months to increased industry recognition of the benefits The SPIRIT Consortium is bringing to re-use of design IP in multi-vendor flows.
The SPIRIT Consortium is attracting new members from a full spectrum of EDA, IP, and system integration companies, ranging from start-ups to industry giants. New additions include the following: Actel, Esterel Technologies, EvatronixSA, Globetech Solutions, GreenSocs, GroupeSilicomp, HDL Design House, MataiTech, Mercury Computer, Systems, MIPS Technologies Inc., Moxon Design, NewLogic Technologies AG, a Wipro Company, Rightec Ltd., Scarlet Code Ltd., SpiraTech Ltd., SyoSil ApS.
The SPIRIT Consortium provides the IP-XACT specification for documenting IP using XML meta-data and interfacing tools using APIs that access design meta-data descriptions of complete system designs. The Consortium tunes the specifications it delivers to the requirements of the industry, and it is focused on enabling technologies for the efficient design of electronic systems from concept to production. It is actively engaged with other standards organizations, building general industry alignment and providing a route to IEEE standardization for the specifications that it produces.
Consortium members are committed to automating the integration of their IP and enabling verifiably consistent design-flows through use of The SPIRIT Consortium specifications. Strengthened with the addition of these new member companies, The Consortium is providing the multi-vendor integration requirements that help ensure efficiency and rapid adoption of its specifications. As The SPIRIT Consortium specifications are adopted, integrated device manufacturers will benefit from faster time-to-market and IP integration by incorporating the IP-XACT standard into their flows. For more information on The SPIRIT Consortium, please visit www.spiritconsortium.org.

********** Products *************
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Statistical Timing Models -- Altos Design Automation Inc. has been formed to develop and market new cell characterization technology and tools for IC designers who are working on complex SoCs (system-on-chip) designs at 90nm, 65nm and 45nm process technologies, with emphasis on the creation of statistical timing models.
The company claims that their solutions run at least an order of magnitude faster than the current generation of in-house and/or commercial cell characterization tools and bring fully-automated vector generation capabilities to IC designers to alleviate the arduous manual setup requirements of many current tools. 
Altos deploys a novel "inside view" approach to characterization where each cell is pre-analyzed to create the optimal vector set and simulation conditions to maximize throughput and ensure full coverage of all logic states. In addition, Altos has integrated its own highly-tuned Spice engine to further reduce the simulation overhead, although 3rd party circuit simulators such as Spectre, Hspice or Eldo are also supported. Altos' "inside view" is especially effective for modeling the impact of random process variation where each transistor within a cell can vary independently. To learn more, visit the company website at: www.altos-da.com.

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DRC Redefined for Nanometer Era -- Mentor Graphics Corporation announced the immediate availability of the Calibre nmDRC tool, which redefines the traditional design rule checking (DRC). It does so by dramatically reducing total cycle time and integrating critical elements such as critical area analysis and critical feature identification, all required to solve the yield challenges of the nanometer era. The tool part of a new platform from Mentor, the Calibre nm Platform. This platform signals a major shift in the way the EDA industry addresses the complexity of nanometer design.

In nanometer technology, physical verification has become a sophisticated, multi-stage process that demands highly integrated approaches to the processing and handling of huge amounts of complex design data. Total cycle time is on the rise due to more complex and larger designs, higher error counts and more verification iterations. Calibre nmDRC responds to the need for reduced cycle time with a revolutionary new approach. It provides four key capabilities, including hyperscaling technology, dynamic results visualization and incremental DRC, integrated design for manufacturing (DFM) analysis, and direct database access.
To ensure high yields when using nanometer process technology, designers require new information and new levels of judgment that go beyond design rule checking to yield analysis. They need new ways to assess the quality of their designs in light of the more complex process constraints and larger process variations they now face. They need new ways to see the impact these constraints and variations have on the quality of their designs. Finally, they need a new kind of work environment that allows them to understand which of these effects is the most important to address during the process of improving design quality. Mentor's answer to this substantial change in the requirements for design signoff is the Calibre nm Platform. To learn more, visit the company website at: www.mentor.com.
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Hybrid Simulator Boosts RTL Simulation -- Liga Systems, Inc. recently emerged from stealth today to unveil NitroSIM, its patented, drop-in Hybrid Simulator that the company claims will boost desktop and compute farm server simulation speed by 10 to 100 times. Hybrid Simulation is a simulation technology harnessing patented software and hardware techniques that enables acceleration of RTL simulation without compromising software simulation features, pricing or capacity. To chip designers, NitroSIM’s very long instruction word (VLIW) turbocharger appears to process the simulation exactly like a standard processor, but orders of magnitude faster and with no change to the existing simulation flow.  The tool eliminates the computation bottleneck in System-on-Chip (SoC) designs of up to 300 million gates – a bottleneck that usually persists even with the use of costly simulation server farms or FPGA- and processor-based hardware accelerators. The tool’s processing power copes easily with increasing work-load, while its simulator-like behavior makes it ideal for use by RTL design, verification, firmware and IP engineers.
Unlike hardware accelerators, NitroSim requires no FPGAs or processors to map the design functionality, as the design is, in its entirety, compiled into memory instructions for execution by the VLIW processor.  With its small form factor, the tool fits inside a desktop or server PC as a plug-in upgrade, requiring no additional space. The tool’s compile and set-up time is on the order of hours and can be applied to all phases of RTL design: from small blocks, to big blocks, to the entire chip, to multi-chip.  This breakthrough solution provides users the ability to simulate and verify entire systems at high simulation speeds at an affordable cost. To learn more, visit the company at: www.ligasystems.com.

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HDL-RTL Tools Team Together -- Concept Engineering said that it employed Verific Design Automation’s hardware description level (HDL) Component Software as the register transfer level (RTL) front end for its newly launched RTLvision PRO. Verific’s Verilog, VHDL and SystemVerilog parsers, analyzers and elaborators were integrated into RTLvision PRO, customizable software to help designers of intellectual property (IP)-based systems on chip (SoCs) reduce the complexity of the debug process. The tools component software packages, which include an RTL database, are written in platform- independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms. All products are licensed as source code and come with online support and maintenance. To learn more about Verific, visit: www.verific.com. To learn more about Concept Engineering, visit: www.concept.de.

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Reduced Area and Design Times -- Synopsys, Inc. just announced that it has expanded its DesignWare Library intellectual property (IP) by adding more than 20 new components. The additions include 10 floating point operations and four complex datapath functions. When used with the company’s Design Compiler synthesis tool, these libraries yields an average reduction of 6% in area and 10% in delay for designs with 20% or greater datapath content. These improvements help reduce design time and risk and improve quality of results (QoR), helping ensure predictable success for complex systems-on-chip (SoC) designs.
New datapath components added to the library, including the floating point family and functions such as blend and saturate, are particularly important because the percentage of datapath content is steadily rising for most computationally intensive designs. In chips for graphics and multimedia processor applications, greater than 50 percent of the die area is devoted to datapath. The new floating point operations are designed for datapath optimization in these important markets.
The library datapath optimizations occur automatically within Synopsys Design Compiler RTL synthesis and concurrently with other logic optimizations, and use the same timing engine to take advantage of the full timing context of the surrounding logic. Correct results can be easily verified using the company’s Synopsys Formality equivalency checking tool. To learn more, visit: www.synopsys.com
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One Transistor, Zero Cap Memory -- Innovative Silicon Inc., the developer of Z-RAM high density memory IP, announced that it will meet with interested designers at DAC. The company helps IC manufacturers reduce the cost of their complex ICs by 10 to 40 percent or more. Its Z-RAM technology is one-fifth the size of embedded SRAM, the most widely used standard on-chip memory technology today, and requires no exotic materials, no extra mask steps and no new physics. In fact, the company claims that there is no other step manufacturers can take that will deliver such dramatic cost savings with so little risk.  In comparison, current embedded DRAM technologies require a capacitor that is extremely difficult to shrink, requiring exotic designs and very expensive process modifications, which makes it very complex to scale to finer geometry process nodes. For more information see http://www.z-ram.com. 

 
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Test and Yield Diagnostics Technology -- Cadence Design Systems, Inc., recently announced it is extending its test and yield diagnostics with new compression and yield diagnostics capabilities. The new release of Cadence Encounter Test addresses the escalating cost of manufacturing high quality silicon with expanded support for non-proprietary, on-chip exclusive-or (XOR) test data compression structures. The new compression capability enables multi-vendor interoperability between Automatic Test Pattern Generation (ATPG) and diagnostics products, and allows the use of a single pass diagnostic flow.
This new test capability supports input side decompression based on an XOR spreading network fan-out, while on the output side, the compression uses XOR tree compaction with optional x-state masking. This augments the company’s OPMISR+ (on-product multiple input shift register) architecture deployed by Cadence Encounter Test customers. To learn more, visit the company website at: www.cadence.com

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