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PCD2 Index


PCD2.A200

A

-12

13.02.1997


-064

Problem : Der RESO-Schalttransistor T1 ist bei Uext ≥30 V und allen Relais geschaltet nicht mehr in Sättigung

Solution : Changed BC846B with BCW66F




PCD2.A220

A

-2

13.02.1997

-064

Problem : Der RESO-Schalttransistor T1 ist bei Uext ≥30 V und allen Relais geschaltet nicht mehr in Sättigung

Solution : Changed BC846B with BCW66F




PCD2.A250

A

-1

29.05.1998

-089

Problem : When output A7 is reset, other outputs may be cleared

Solution : Addition of a wired signal diode (1N4848)

Communication 98052

PCD2.A400

B




13.02.1995

20.06.1997




Typical output delay : 10 μs - switch on delay (prior 10 μs)

50 μs - switch off delay (prior 5 μs)
Leakage current : max. 0.1 mA (prior 1 mA)

Version A was equipped with bipolar transistors wihich have a shorter switch off delay (5 μs), but a larger voltage drop (1 V at 0.5 A).

PCD2.A410

A

-1

22.12.2003

-188

TLP127-4 obsolete. Replaced by 4xTLP127




PCD2.A465

A

-1

19.11.1999


-133

Problem : Risk of short circuit during insertion of modules

Solution : it is advisable to shorten the projecting contact pins

SAIA°Bulletin 99-4

PCD2.B100



















PCD2.C2000

C




22.9.10

PC-0464

Problem: wide spread of measured analog values

Solution: with new Version C, the value is stable (stronger supply filtering)

no customer complaint, was internally found

PCD2.E500

B

2,3

7.2.2012

pc-0574

Schaltzeit angepasst




PCD2.E165

A

-1

19.11.1999


-133

Problem : Risk of short circuit during insertion of modules

Solution : it is advisable to shorten the projecting contact pins

SAIA°Bulletin 99-4

PCD2.E610

B

-15

12.10.1999

-129

Problem : Equipped with wrong optocoupler

Solution : Changed PC 355 to PC357NT




PCD2.E61x

B

-1

31.10.1999


-120

Problem : Optocoupler PC3Q15 not available anymore

Solution : Changed optocoupler type to PC355 NT




PCD2.E61x

B




30.06.1997




Input current : for source operation 5.0 mA (prior 12.0 mA)

(at 24 VDC) for sink operation 3.7 mA ( prior 5.5 mA)

Typical input delay : E610 10/10 ms (prior 8/8 ms)

(low-high / high-low) E611 0.2/1.0 ms (prior 0.1/0.3 ms)




PCD2.F2810

D




08.11.2010

PC-0492

New FW V020 compatible with the Modbus driver




PCD2.F2xx0

D




08.11.2010

PC-0492

New FW V020 compatible with the Modbus driver




PCD2.F510,

520,530

J




16.02.2007

---

see Version H 1, new drill diameter 3.95 for fixing on plastic holder

(AD-PC-07-112)




PCD2.F520

/530

H

-1

26.03.2004

-186

Problem: On power-up the oscillator sometimes did not start

Solution: 180k parallel to quartz

solved on Version J with LP index d

PCD2.F5x0

H




01.01.1998


-072

These modules, on the hardware prior to version “H”, were equipped with the RTC; since beginning of 1998 the RTC is accommodated directly to the base unit of the PCD2.M1x0.

EA 072 from PCD2

PCD2.G400

C




06.01.2006

-220

Modif.3 auf neuer LP realisiert




PCD2.G400

B

-1,2,3

22.11.2005

-220

Problem: PCD2.M480: Reflexionen auf dem I/O Bus in Zusammenhang mit Erweiterung generieren ‚falsche’ Clock Impulse  Falsche Digitalwerte

Lösung: Filter – Kondensator auf Clock – Signal anbringen. Dadurch werden kurze Pulse unterdrückt.
 Siehe EA-EPCD2-220

Wird korrigiert mit neuem Leiterplatten - Index

PCD2.G410

C




06.01.2006

-220

Modif.3 auf neuer LP realisiert




PCD2.G410

B

-3

22.11.2005

-220

Problem: PCD2.M480: Reflexionen auf dem I/O Bus in Zusammenhang mit Erweiterung generieren ‚falsche’ Clock Impulse  Falsche Digitalwerte

Lösung: Filter – Kondensator auf Clock – Signal anbringen. Dadurch werden kurze Pulse unterdrückt.
 Siehe EA-EPCD2-220

Wird korrigiert mit neuem Leiterplatten - Index

PCD2.H100

A

-1

29.03.1999


-116

Problem : Counting frequency adapted

Solution : C13 changed to 1.5 nF




PCD2.H110


C




04.10.2002




New FPGA HC3




PCD2.H150


A

-1

05.05.2004

-192

TVS 5V anstelle 8V. Protects RS422 better




PCD2.H150


A




02.05.2001




New FPGA HE3. No functional changes prior to HE2. Only for production




PCD2.H150


A




18.01.1999

-111

New FPGA HE2 (prior was HE1)

Status 29.04.99

Stock 79 HM HE1

PCD2.H210


B




01.02.07

-0256

New FPGA HD7(prior was HD6)




PCD2.H210


B




14.01.03

2-180

New FPGA HD6 (prior was HD5)

officialized 10.3.03 TM 61278

PCD2.H210


B




06.05.1998

-091

New FPGA HD5 (prior was HD4)




PCD2.H210








24.03.1998




New FPGA HD4 (prior was HD3)




PCD2.H210








25.02.1998




New FPGA HD3 (prior was HD2)




PCD2.H210








09.02.1998




New FPGA HD2 (prior was HD1)




PCD2.H222

B




27.04.2010




New schema and layout to fulfil emc conformity




PCD2.H310


A

-12

18.06.1999

-122

New input filter (only on index)

Since 07.09.00

Corrected on version “B”

PCD2.H311


A

-12

01.08.1999

-123

New input filter (only on index)

Corrected on version “B”

PCD2.H31x


A

-1

11.06.1997

-067

Problem : Amélioration du signal d’horloge (6 MHz)

Solution : Suppression d’une capacité de 33 pF (le C3)



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